Although a plurality of special purpose LSIs (ASICs) are used in an apparatus such as a home electric appliance, an AV apparatus, a mobile phone, an automobile, and an industrial machine, the special purpose LSI is an essential component for high performance, advanced function, miniaturization, low power consumption, and cost reduction in an apparatus. In recent years, a reliability problem that a transient failure (soft error) with radiation is likely to occur due to micro-fabrication of a semiconductor process. A static random access memory (SRAM) which is a volatile memory which does not require regular refreshing (storing and maintaining operation) is built-in an LSI such as a microprocessor, a microcontroller, and an AISC as a data storage memory other than a memory chip of a single unit, however, the SRAM is known to have a soft error resistance lower than that of a device such as a combination circuit or a flip flop.
An error detection and correction technique called an error correction code (ECC) is generally used as a countermeasure to the soft error of the SRAM. A redundant code portion is added to the SRAM, a redundant code is generated at the time of data write and stored together with data, the error detection and correction is performed using the data and redundant code at the time of data read. In a scheme called a single error correction and double error detection (SECDED), 1-bit error correction and 2-bit error detection are possible.
When micro-fabrication of semiconductor process is further progressed, it is known that the soft error becomes a problem in a sequential circuit such as a flip flop. Although a situation in which a soft error occurs in a flip flop included in a logic circuit and the logic circuit operates erroneously to cause an erroneous access to the SRAM is considered, in such a case, it is unable to detect and correct an error by the ECC.
Furthermore, contrary to the ASIC in which an internal logic circuit is fixed, a field programmable gate array (FPGA) which is a programmable device in which the internal logic circuit may be defined and changed by a user maintains logic circuit information within a configuration RAM (CRAM) and thus, there is a problem that the soft error occurs in the CRAM, logic circuit information is written and altered, and the logic circuit is changed to malfunction (failed) and erroneously operates.
There is triple modular redundancy as a method not causing an erroneous output even when a logic circuit is failed. The outputs of logic circuits of triple modular redundancy are subjected to majority decision processing and when results of the majority decision processing become a two to one ratio, a majority side that two results coincide with each other is selected. RAM access signals of the logic circuit are subjected to the majority decision processing to thereby make it possible to mask an erroneous access and perform a normal access.
In Non-Patent Literature 1, a method called “TMR block RAM with refresh” is suggested as an error correction method of a block RAM (BRAM) which is a built-in memory of the FPGA. In this method, one port of two access ports of the BRAM is used for accessing a logic circuit and the other port is used for error correction. The BRAM is connected each of the logic circuits of triple modular redundancy and a BRAM refresh circuit is connected to the port for error correction. The BRAM refresh circuit reads data from the same address of three BRAMs simultaneously, performs the majority decision processing on the data, and writes back the data irrelevantly to an access to the logic circuit. Accessing to the BRAM is executed while updating an address periodically.